object
CacheIvy
Value Members
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final
def
!=(arg0: AnyRef): Boolean
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final
def
!=(arg0: Any): Boolean
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final
def
##(): Int
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final
def
==(arg0: AnyRef): Boolean
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final
def
==(arg0: Any): Boolean
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object
L1
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object
L2
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object
L3
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object
L4
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object
L5
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implicit
def
artifactFormat(implicit sf: Format[String], uf: Format[Option[URL]]): Format[Artifact]
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implicit
def
artifactIC: InputCache[Artifact]
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final
def
asInstanceOf[T0]: T0
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implicit
def
authIC: InputCache[SshAuthentication]
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implicit
def
callerFormat: Format[Caller]
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implicit
lazy val
chainedIC: InputCache[ChainedResolver]
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implicit
def
classpathFormat: Format[Map[String, Seq[File]]]
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def
clone(): AnyRef
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implicit
def
confIC: InputCache[Configuration]
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implicit
def
confReportFormat(implicit m: Format[String], mr: Format[Seq[ModuleReport]], oar: Format[Seq[OrganizationArtifactReport]]): Format[ConfigurationReport]
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implicit
def
configurationFormat(implicit sf: Format[String]): Format[Configuration]
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implicit
def
connectionIC: InputCache[SshConnection]
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implicit
def
crossVersionFormat: Format[CrossVersion]
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implicit
def
crossVersionIC: InputCache[CrossVersion]
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final
def
eq(arg0: AnyRef): Boolean
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def
equals(arg0: Any): Boolean
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lazy val
excludeMap: Format[Map[ModuleID, Set[String]]]
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implicit
def
exclusionIC: InputCache[InclExclRule]
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implicit
def
exclusionRuleFormat(implicit sf: Format[String]): Format[InclExclRule]
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implicit
def
extIvyIC: InputCache[ExternalIvyConfiguration]
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implicit
def
fileConfIC: InputCache[FileConfiguration]
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def
finalize(): Unit
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final
def
getClass(): Class[_]
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def
hashCode(): Int
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implicit
def
inlineIC: InputCache[InlineConfiguration]
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final
def
isInstanceOf[T0]: Boolean
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implicit
def
ivyConfigurationIC: InputCache[IvyConfiguration]
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implicit
def
ivyFileIC: InputCache[IvyFileConfiguration]
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implicit
def
ivyPathsIC: InputCache[IvyPaths]
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implicit
def
ivyScalaIC: InputCache[IvyScala]
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implicit
def
moduleConfIC: InputCache[ModuleConfiguration]
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implicit
def
moduleIC: InputCache[ModuleID]
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implicit
def
moduleIDFormat(implicit sf: Format[String], bf: Format[Boolean]): Format[ModuleID]
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lazy val
moduleIDSeqIC: InputCache[Seq[ModuleID]]
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lazy val
modulePositionMapFormat: Format[Map[ModuleID, SourcePosition]]
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implicit
def
moduleReportFormat(implicit cf: Format[Seq[Caller]], ff: Format[File]): Format[ModuleReport]
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implicit
def
moduleSetIC: InputCache[Set[ModuleID]]
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implicit
def
moduleSettingsIC: InputCache[ModuleSettings]
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def
names(s: Iterable[Configuration]): Set[String]
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final
def
ne(arg0: AnyRef): Boolean
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final
def
notify(): Unit
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final
def
notifyAll(): Unit
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implicit
def
organizationArtifactReportFormat(implicit sf: Format[String], bf: Format[Boolean], df: Format[Seq[ModuleReport]]): Format[OrganizationArtifactReport]
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def
password(s: Option[String]): Array[Byte]
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implicit
def
patternsIC: InputCache[Patterns]
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implicit
def
pomIC: InputCache[PomConfiguration]
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implicit
lazy val
resolverIC: InputCache[Resolver]
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implicit
def
retrieveIC: InputCache[RetrieveConfiguration]
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implicit
def
sbtExclusionIC: InputCache[SbtExclusionRule]
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implicit
def
sourcePositionFormat: Format[SourcePosition]
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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def
toString(): String
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implicit
def
updateConfIC: InputCache[UpdateConfiguration]
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lazy val
updateIC: InputCache[internal.util.Types.:+:[IvyConfiguration, internal.util.Types.:+:[ModuleSettings, internal.util.Types.:+:[UpdateConfiguration, HNil]]]]
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implicit
lazy val
updateReportFormat: Format[UpdateReport]
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implicit
def
updateStatsFormat: Format[UpdateStats]
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final
def
wait(): Unit
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
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implicit
def
wrapHL[W, H, T <: HList](implicit f: (W) ⇒ internal.util.Types.:+:[H, T], cache: InputCache[internal.util.Types.:+:[H, T]]): InputCache[W]
InputCaches for IvyConfiguration, ModuleSettings, and UpdateConfiguration The InputCaches for a basic data structure is built in two parts. Given the data structure: Data[A,B,C, ...] 1) Define a conversion from Data to the HList A :+: B :+: C :+: ... :+: HNil, excluding any members that should not be considered for caching 2) In theory, 1) would be enough and wrapHL would generate InputCache[Data] as long as all of InputCache[A], InputCache[B], ... exist. However, if any of these child InputCaches are constructed using wrapHL, you get a diverging implicit error. (I believe scalac is generating this error as specified, but that the implicits would be valid and not be infinite. This might take some effort to come up with a new rule that allows this) 3) So, we need to explicitly define the intermediate implicits. The general approach is:
Each Data in LN only uses implicits from L(N-1). This way, higher levels (higher N) cannot see the HList conversions of subcomponents but can use the explicitly defined subcomponent implicits and there is no divergence. 4) Ideally, diverging implicits could be relaxed so that the ... = wrapIn lines could be removed.